Requirements
Market · product standards · ports · performance criteria
ENGINEERING FLOW
01Understand→
02Control→
03Verify→
04Resolve→
05Document
DESIGN SYSTEM / ENGINEERING-LED
Make EMC decisions before the first layout.
Use schematic and PCB methods from the core reference to organize six design domains into a reviewable, verifiable, and regression-ready engineering system.
ENERGY / RETURN / COUPLING / PROOF01 / DESIGN GATES
Each development gate leaves different evidence.
EMC is not a post-layout check. It begins with requirements and architecture and continues through production changes.
Architecture
Noise sources · sensitive domains · chassis and harness topology
Schematic
Edge control · filtering · isolation · clamping · provisions
PCB
Stackup · return paths · hot loops · interfaces · shield termination
Prototype
Baseline spectrum · near-field map · common-mode current · immunity threshold
Compliance
Worst-case modes · margin · reports · change regression
01 / POWER / HOT LOOPPOWER / HOT LOOP
Power and switching nodes
How small is the high-di/dt loop, and how large is the high-dv/dt copper area?
- 01Input hot loop
- 02Gate edge and ringing
- 03Common- and differential-mode paths
- 04Decoupling and power impedance
02 / CLOCK / SPECTRUMCLOCK / SPECTRUM
Clocks and digital edges
Is emission bandwidth governed by clock frequency or edge rate?
- 01Edge rate
- 02Harmonic relationships
- 03Source damping
- 04Clock and interface isolation
03 / STACKUP / RETURNSTACKUP / RETURN
Stackup and return continuity
Does every critical trace have an adjacent, continuous reference through layer transitions?
- 01Continuous reference planes
- 02Return vias at transitions
- 03No routing across splits
- 04Functional zoning without split grounds
04 / I/O / COMMON MODEI/O / COMMON MODE
High-speed I/O and cables
Where can differential imbalance convert into cable common-mode current?
- 01Differential symmetry
- 02Connector reference
- 03Evidence-based CMC selection
- 04Chassis transition
05 / TRANSIENT / DIVERSIONTRANSIENT / DIVERSION
ESD, EFT, and surge
Can pulse current be diverted through a short, wide path before it reaches sensitive circuitry?
- 01Protection device selection
- 02Flow-through placement
- 03Discharge reference
- 04Isolation capacitance
06 / SHIELD / APERTURESHIELD / APERTURE
Shielding, apertures, and enclosure
Which seam interrupts surface current, and where does the cable shield terminate?
- 01Long-seam control
- 02360° shield termination
- 03Seam impedance
- 04PCB-to-chassis coordination
02 / EDGE BANDWIDTH
Control the source before designing the path.
The edge-spectrum model turns clock, damping, and component-substitution risk into discussable quantities.
EDGE → SPECTRUM
A low fundamental can still have a fast edge.
Use fedge ≈ 1/(πTr) to estimate the trapezoidal edge-spectrum breakpoint. It is not a hard cutoff; package, drive impedance, ringing, and duty cycle alter the measured spectrum.
TRAPEZOIDAL ENVELOPE · ESTIMATE
318fedge MHz3odd harmonics in-band
f₀Ideal 50% duty cycle · odd harmonics only · additional envelope decay above breakpoint2450 MHz
03 / RETURN CONTINUITY
Signals follow traces. Current follows loops.
Plane splits, layer transitions, and vias are not isolated rules; each changes high-frequency return geometry and impedance.
RETURN PATH / EXPLAINER
Signals follow traces. Current follows loops.
SOURCEDRIVER
VICTIMRECEIVER
REFERENCE PLANE
FORWARD CURRENTRETURN CURRENT
Example loop area10 mm²Electrical path size L/λ0.042Geometry stateNon-negligible
Example geometry: 50 mm signal length and 0.2 mm reference spacing; the split case uses a 20 mm detour width and 110 mm return path. Real current distribution requires stackup-aware 3D analysis or measurement.
04 / REAL COMPONENTS
A filter is not a schematic symbol. A component is not an ideal model.
Self-resonance and parasitics determine whether a component behaves as capacitance, inductance, or a new resonance in the target band.
REAL CAPACITOR IMPEDANCE45.9 MHzSELF-RESONANCE
FILTERS ARE FREQUENCY-DEPENDENT
Above self-resonance, a capacitor begins to behave like an inductor.
This is why more capacitance does not necessarily improve high-frequency EMI. Component, package, layout, source impedance, and load impedance must be verified together.
05 / TRANSIENT DIVERSION
Protection-device placement is part of the protection strategy.
Place the TVS in the complete diversion loop to evaluate residual voltage among connector, chassis, and sensitive IC.
PORT
TVS
SENSITIVE IC
CHASSIS / PGND
8 kVCONTACT EVENT
PROTECTION TOPOLOGY
Intercept at the entry and divert through a short, wide path.
The protection device sits at the connector, so current reaches the TVS before the protected trace and the diversion loop avoids sensitive circuitry.