CORE ENGINEERING REFERENCE

One reference system establishes the site's engineering coordinate system.

Start with energy and complete current loops, then move into schematics, PCB geometry, interfaces and test cases. Global primary sources add evidence, boundaries and standards status without changing this physical spine.

04engineering layers02interactive models06closed-loop cases

Read the engineering reference ↗Review the editorial method

EMCSOURCE / PATH / VICTIM

PHYSICS / DESIGN / PCB / VERIFICATION

01 / DOCUMENT SPINE

Progress through four layers from concepts to cases.

Each layer answers a different question: why it happens, how to design, how to implement and how to verify.

01P01—24

Physical foundations

Explain behaviour through edges, return paths and coupling

Voltage transients
Signal return paths
Common / differential mode
Reflection and crosstalk
High-frequency component models

02P25—39

Schematic design

Create controlled paths for interference current

ESD protection
Grounding and isolation
Shielding and filtering
Impedance matching
Bus design

03P39—56

PCB design

Implement return-path continuity in physical geometry

Stack-up and placement
Differential routing and tuning
Vias and decoupling
Layer-transition returns
Connectors

04P57—63

Closed-loop cases

Verify with frequency, paths and single-variable experiments

399 MHz
375 MHz
466 MHz
EFT common-mode current
TVS placement

FOUNDATION / RETURN CURRENT

02 / CENTRAL IDEA

The central idea: draw the complete current loop first.

Forward and return paths jointly determine impedance, radiation and immunity. Ground is not a symbol but a frequency-dependent current path; splits, layer transitions, connectors and protection devices belong in the same closed-loop analysis.

RETURN PATH / EXPLAINER

Signals follow traces. Current follows loops.

SOURCEDRIVER

VICTIMRECEIVER

REFERENCE PLANE

FORWARD CURRENTRETURN CURRENT

Model frequency 250 MHz

Example loop area10 mm²Electrical path size L/λ0.042Geometry stateNon-negligible

Example geometry: 50 mm signal length and 0.2 mm reference spacing; the split case uses a 20 mm detour width and 110 mm return path. Real current distribution requires stackup-aware 3D analysis or measurement.

03 / TWO FAILURE MODES

One failure detours the return; the other lengthens the discharge path.

They look different but share one mechanism: RF impedance pushes current into an unintended path. The interactive models turn static guidance into an operable decision.

PORT

TVS

SENSITIVE IC

CHASSIS / PGND

8 kVCONTACT EVENT

PROTECTION TOPOLOGY

Intercept at the entry and divert through a short, wide path.

The protection device sits at the connector, so current reaches the TVS before the protected trace and the diversion loop avoids sensitive circuitry.

DIFFERENTIAL BALANCE / COMMON-MODE CONVERSION

04 / DIFFERENTIAL SIGNAL

Differential signalling is not immunity; symmetry is the asset.

Pair length, spacing, reference plane and adjacent geometry jointly determine common-mode conversion. A continuous reference remains essential because any asymmetry leaves a common-mode component that must return.

Explore differential and high-speed interface resources ↗

05 / SIX CLOSED-LOOP CASES

Build hypotheses from frequency; converge with single-variable experiments.

Each case connects frequency relationships, physical paths, verification actions and the final redesign, turning experience into reusable engineering evidence.

C01399 MHz

133 MHz × 3

Clock coupling near a differential pair

DiagnosisCLK133 runs parallel to the USB differential pair over a long distance with asymmetric via geometry.

ActionIncrease spacing between the clock route, the differential pair and their vias.

C02EDGE

Component-lot change

Faster edges in a replacement interface device

DiagnosisFunction is unchanged, but faster edges in the new lot extend EMI bandwidth.

ActionInclude component substitutions in power, signal-integrity and EMC regression tests.

C03375 MHz

LED trace

Ethernet indicator trace crosses a plane split

DiagnosisThe panel LED signal carries internal noise to the RJ45 and external cable.

ActionRestore the reference and bridge return, then slow and filter the source edge.

C04466 MHz

155.52 MHz × 3

Clock and interface IC share a supply

DiagnosisClock-driver noise enters the interface IC through shared supply impedance and radiates from the cable.

ActionIsolate the clock supply domain and verify supply impedance and common-mode current.

C05EFT/B

Optocoupler parasitic capacitance

Isolation does not mean zero current

DiagnosisFive optocouplers provide roughly 10 pF of aggregate parasitic capacitance and form a common-mode path.

ActionProvide a controlled common-mode bypass and reduce digital-ground path impedance.

C068 kV

Long TVS branch

Protection device placed on a long branch

DiagnosisA TVS far from the main path adds branch inductance and raises residual voltage at the sensitive node.

ActionPlace the TVS at the connector with flow-through routing and a short discharge loop.

06 / GLOBAL EVIDENCE LAYER

Primary global sources calibrate the boundaries of the engineering spine.

Each supplementary source closes one defined gap: edition status, test boundary, component parameter or modern high-speed layout.

01RETURN PATH

Continuous reference planes and shortest return paths

TI SCAA082A ↗02HIGH-SPEED I/O

High-speed interfaces and flow-through ESD layout

TI SPRAAR7J ↗03SYSTEM ESD

TLP data, device parameters and system-level protection

Nexperia ↗04GROUND / CABLE

Return-current spreading and cable common-mode noise

Murata ↗